fpga

All Aboard the Small Form Factor Express

COM Express

Big is beautiful – or so we are told. But now it looks like small and petit is well and truly back in fashion.

SWAP – Size Weight And Power is the driving force behind many embedded applications today and low power, and often small footprint, processors such as those made by UK based ARM and Intel’s ATOM enable designs to shrink to very small proportions.

COM Express was ratified by PICMG in 2005, but now 6 years later the COM Express Mini / Ultra (or Nano ETX Express as Kontron would have us call it) is here and its tiny!

This new form factor is about the size of a credit card, specifically 55mm x 84mm and can have one of 2 connector configurations defined by the COM Express standard; both using a 220 pin connector.

• Type 1: Single connector (220 pin), 6 PCI Express lanes, no PEG, no PCI, no IDE, 4 SATA, 1 LAN
• Type 10: Single connector (220 pin), 4 PCI Express lanes, no PEG, no PCI, no IDE, 2 SATA, 1 LAN, single channel LVDS only, DDI, no VGA, 2 Serial COM

As you can see the focus is high speed PCI Express and Type 1 has 6 PCI Express lanes. But the more popular Type 10 maximises the variety and has a lower 4 PCI Express Lanes but adds Serial COMS, DDI (digital display interface) and LVDS.

A custom carrier board will need to be designed by the OEM to host the COM Express module but this can easily remain in the small footprint allowing the form factor to be used in ultra small, mobile and hand held applications. This enables new application opportunities that were previously inhibited by size, weight or power restrictions.

Applications – robotics, UAV, communications, computing, EPOS, handheld terminals and small rugged computers.

XPand6001 - Extreme Engineering

Sarsen Technology Limited is currently reviewing a range of COM Express modules for the UK market; if you have a project requirement or would like to know more about small form factor boards and chassis please get in touch via the website.

Links/References:
ARM – http://www.arm.com
ATOM – http://www.intel.com/…
Extreme Engineering – http://www.x-es.com
Image Credit – www.kontron.com

What is an FPGA?

What is an FPGA?

Increasingly FPGAs have gained popularity in the embedded market space to speed up development and for rapid prototyping of complex systems. But what is an FPGA? Here is a very good explanation from market leader Altera.

The field-programmable gate array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows you to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field—hence the name “field-programmable”. You can use an FPGA to implement any logical function that an application-specific integrated circuit (ASIC) could perform, but the ability to update the functionality after shipping offers advantages for many applications.

Unlike previous generation FPGAs using I/Os with programmable logic and interconnects, today’s FPGAs consist of various mixes of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. Specifically, an FPGA contains programmable logic components called logic elements (LEs) and a hierarchy of reconfigurable interconnects that allow the LEs to be physically connected. You can configure LEs to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flipflops or more complete blocks of memory.

As FPGAs continue to evolve, the devices have become more integrated. Hard intellectual property (IP) blocks built into the FPGA fabric provide rich functions while lowering power and cost and freeing up logic resources for product differentiation. Newer FPGA families are being developed with hard embedded processors, transforming the devices into systems on a chip (SoC).

Compared to ASICs or ASSPs, FPGAs offer many design advantages, including:

• Rapid prototyping
• Shorter time to market
• The ability to re-program in the field for debugging
• Lower NRE costs
• Long product life cycle to mitigate obsolescence risk

Source : http://www.altera.com/

Epiphany Architecture Promises Massive Floating-Point Gains

Epiphany Architecture

Earlier this month BittWare announced “A New Approach to Floating Point DSP” with the release of the Anemone Co-Processor. The Anemone floating point co-processor chip is designed for use with Altera’s high performance FPGAs. OEM’d from Adapteva’s new Epiphany architecture, BittWare’s Anemone chip is a scalable, true C-programmable, floating point engine that enables novel solutions for complex and evolving signal processing applications.

It’s something which has already caught the eye of FPGA and DSP specialist BittWare, which has licensed Adapteva’s Epiphany technology for use in its own Altera-based FPGAs under the name Anemone. “We believe that Adapteva’s Epiphany architecture represents a flash of brilliance that reintroduces some much needed creativity into the embedded signal processing world,” BittWare’s chief Jeff Milrod crowed at the launch of Anemone. “The resulting Anemone chip, combined with Altera’s family of FPGAs, creates an insanely cool solution for complex signal processing tasks that can be optimised for power, performance, and productivity.”

So what is Epiphany? Here’s the opening section of an interview with Andreas Olofsson of Adapteva with THINQ:

While chip giants ARM, Intel, and AMD battle for control of your smartphones and PCs, a small company in Massachusetts called Adapteva is starting a revolution: many-core processors that offer a significant performance boost over anything currently on the market. We chat to its founder Andreas Olofsson to find out what’s going on.

Initially, it’s easy to dismiss Adapteva’s chances of success as slim to none: in markets where a single processor architecture holds overwhelming dominance, such as x86 in mainstream computing and ARM in the world of smartphones, Olofsson has decided to develop an entirely new architecture.

Olofsson readily admits that history is littered with companies who have tried the same approach and failed. “In the mobile space there’s MIPS, for example,” he explained to thinq_ during our interview. “That’s another architecture, which has been around for 25, 30 years now – you know, it’s a great architecture, and yet they have very low traction. Everybody – 98 per cent of the market – uses ARM.”

To avoid falling into the same trap, Olofsson has a new idea – or, specifically, a variation on an old one. In the early days of personal computing, it was common for a central processor to have a ‘math co-processor’ chip alongside it – a secondary processor which was designed specifically to carry out floating point arithmetic at speeds significantly faster than the main processor. Intel had its 8087, Motorola its 68881, and AMD the stand-alone 9511.

Over time, however, these chips became integrated into the processor itself – evolving into the high-performance floating-point units, or FPUs, that are a feature of all modern central processors. Olofsson’s big idea, he explained, is to bring the days of the math co-processor back – and promises some major performance-per-watt gains for those making the step.

Read more / Source – THINQ

See Also – Wall Street Journal, BittWare Anemone, Adapteva

Anemone Co-Processor for FPGAs, BittWare Inc

Anemone Co-Processor for FPGAs

SAN JOSE, CALIFORNIA – May 3, 2011 – BittWare announced today, at the Embedded Systems Conference, the Anemone floating point co-processor chip for use with Altera’s high performance FPGAs.

Read the Full Press Release here: http://www.bittware.com/media/press/pr.cfm?id=62

BittWare yesterday introduced Anemone to the Embedded Systems Conference. What is it?

Its a Floating Point Co-Processor for FPGAs. Anemone represents a new hybrid approach for floating point signal processing that adds a low-power, C-programmable compute engine to world-class FPGA technology from Altera.

Features

• 16 independent floating point cores
• 32 GFLOPS of floating point processing
• 2 Watts total chip power
• ANSI C-programmable
• IEEE Floating Point
• Shared memory architecture
• External I/O via memory-mapped links
• Scale multiple chips up to 8 TFLOPS
• High throughput mesh network
• Standard GNU/Eclipse Development Tools
• Available from BittWare on standard board formats

For more information – visit the Anemone page on BittWare’s website.

Traditional floating point DSPs, while excellent at complex processing tasks, have limitations when it comes to chip real estate and power efficiency that have caused them to become an endangered species. And FPGAs, while superior for versatility and configurability, can be difficult to use for complex and evolving applications. The BittWare Anemone, featuring the Epiphany architecture from Adapteva, enables the best assets of both to be combined, thereby offering a completely new approach to floating point digital signal processing. This hybrid solution provides a standard processor software development environment working in conjunction with a world-class FPGA platform, allowing users to optimally partition their algorithms into hardware and software. The result is superior development productivity and unmatched system size, weight, and power.

Focus on power & efficiency

Anemone is a truly C-programmable floating point compute engine. It is unique in that it achieves superior power efficiency and processing performance because it is designed to work alongside an FPGA as a co-processor. The FPGA handles all the memory, I/O interfacing, protocol processing, and special functions in addition to any computational tasks it may perform, leaving the Anemone free to efficiently perform the complex processing tasks that DSPs are ideal for. This allows Anemone to be an extremely efficient chip – as compared with traditional floating point DSPs that may only use 5% of the silicon area for processing.

Simple, elegantly designed floating point cores

The Anemone is a completely scalable 1 GHz multicore processor with 16 eCores that provide a total sustained performance of 32 GFLOPS while consuming only 2 Watts of total chip power. Each eCore features a compact, general-purpose instruction set that requires no instruction level parallelism and provides high program efficiency. All floating point computations are performed as single-precision IEEE 754; hardware looping is also supported. Anemone offers distributed and segmented memory, and large uniform register files. On-chip distributed shared memory is 4 Mb (32 KByte per eCore) with 32 GBytes/sec of sustained memory bandwidth within each eCore. The cache-less shared memory architecture is extended off-chip via I/O links.

High-throughput eMesh network

The Anemone features an internal high-throughput mesh network, with separate data paths for on-chip and off-chip communications. Each eCore has a multi-channel DMA engine to support background data movement over the mesh. Total on-chip, inter-core bandwidth is 128 GBytes/sec full duplex, with an additional 8 GBytes/sec of off-chip bandwidth. Each router node can simultaneously sustain full-duplex transfers on all ports, with automatic routing based on global addressing.

I/O via memory-mapped high-speed links

The Anemone provides a flexible low-overhead external interconnect scheme that supports memory-mapped direct connection of multiple Anemones and is compatible with any LVDS capable FPGA. This is achieved via four links that are full-duplex 8-bit LVDS data ports @ 500 MHz DDR, each simultaneously providing 1 GByte/sec in each direction for a total off-chip bandwidth of 8 GBytes/sec. Its FPGA co-processor use model provides the ultimate flexibility: since all external I/O goes through an FPGA, system designers can customize the I/O to their application’s specific requirements.

ANSI C-programmable; Standard GNU development tools

The Anemone reduces system development cost by enabling out-of-the-box execution of applications written in regular ANSI-C. It does not require any C-subset, language extensions, or SIMD. Standard GNU development tools are supported including an optimizing C complier, simulator, GDB debugger, and Eclipse multi-core IDE.

MP32: First Soft Processor Supporting MIPS and VxWorks

MP32 is a royalty-free soft core processor from ALTERA, allowing you to easily increase performance by adding as many MP32 processors as you can fit on your FPGA.

What makes the MP32 processor ideal for your custom embedded applications?

• It’s the first MIPS^®-compatible soft processor.
• It runs Wind River’s VxWorks real-time operating system, so you can use familiar tools and middleware.
• It’s optimized for Altera^® FPGAs and HardCopy^® ASICs, including previous-generation and future devices.

SOURCE: MP32: First Soft Processor Supporting MIPS and VxWorks.

Faster Time to Market

A flexible, applications-class processor, MP32 brings with it the expansive MIPS ecosystem of software and tools. This includes intellectual property (IP) cores for embedded processing, protocols, memory control, and applications including video, digital signal processing, and networking.

You’ll get faster time to market because you can reuse a lot of IP—including your own. You’ll also experience faster system integration because you can use our common FPGA design flow, based on Qsys. The Qsys system integration tool, available in Quartus^® II software, automatically generates interconnect logic to connect IP functions and subsystems.

Since you can reuse software you’ve already written for your MIPS processor, you’ll be able take advantage of the code, IP, and expertise your team already has.

Altera Breaks Semiconductor Industry Record

Altera Stratix V FPGA

Altera Breaks Semiconductor Industry Record for Most Transistors on an Integrated Circuit – and delivers the industry’s highest bandwidth, highest performance FPGA, featuring a record setting 3.9 Billion transistors!

San Jose, Calif., April 18, 2011 – Altera Corporation (Nasdaq: ALTR) today announced it set an industry milestone in semiconductor technology by delivering the most transistors ever packed onto an integrated circuit. Altera’s 28-nm Stratix V FPGAs are the semiconductor industry’s first devices to feature 3.9 billion transistors. This level of functionality delivers unparalleled performance to system designers.

Read the Full Press Release Here  &  The Stratix V data on the Altera Website Here.

A Match Made in Silicon Heaven?

A configurable Intel Atom processor with an on-package Altera FPGA

I stumbled across this article the other day and it got me thinking about what a big partnership this is and what impact it will have on the embedded world.

E600 brings everything onboard for the platform, including PCI-E for using the E600 in a multitude of different capacities. Either bring your own PCH or build one yourself – Intel already showed examples of Realtek, OKI, and ST Microelectronics on stage. If you’re just building a desktop, Intel has a fairly standard platform controller hub called the EG20T for control like ethernet, SATA and USB. Intel really hopes that their embedded Atom platform will bring cost of system integration way down.

Ok So its a new ATOM CPU so what?

When designing a microprocessor you have two options. For very complex designs you have a bunch of engineers come up with an architecture. They then spend countless hours, days, months, eons designing it, and doing layout and performance optimization. Photolithographic masks are made and handed off to a fab that produces the silicon on wafers. This is a great approach for microprocessors that have high complexity, performance and volume demands. If you have a simpler design and want to get it to market cheaper, there’s another option: a FPGA.

A field programmable gate array is exactly what it sounds like, a whole bunch of gates on a die that can be programmed in the field. An FPGA can be made to function like pretty much whatever microprocessor design you program it to be. You shave off the initial manufacturing costs as you don’t need to make expensive masks. FPGAs are often used in emulating larger microprocessor designs.

As Intel tries to take the Atom into the embedded space it may run into some customers that want to pair Atom with custom hardware. Intel could simply make a version of Atom for every single market vertical, however that would incur a significant cost overhead. 

Instead, in the first half of 2011 Intel will introduce the Stellarton processor. It’s a configurable Intel Atom processor with an on-package Altera FPGA.

The theory sounds great but in practice this could be tricky device to integrate – don’t you think?

SOURCE – AnandTech , SLASHGEAR, Intel

Altera Wants You…

Altera Corp want your opinions and input. Set up in 2010 the Altera Wiki was founded to provide a website for Altera users to contribute technical how-to articles and share their projects and IP with the community for all Altera related topics. The Altera Wiki complements the Altera Forum site. The Altera Forum is still the site to use for Question and Answer community help using thread discussions.

The Altera Wiki is a dynamic library of public articles that any and all can update and contribute. They have integrated the Nios Wiki into the Altera Wiki, including all pages and usernames. If you have any trouble accessing your account, please contact the Admin (wikiadmin ‘at’ alterawiki ‘dot’ com). To be a contributor to existing or create new article or project share, just register for a free account and sign in.

What is a WIKI?

A wiki is a collaborative Web site oriented to providing knowledge in a particular domain. Anyone can enter information, or change or comment on anyone else’s contributions. A wiki website allows communities to easily create and edit web pages via a web browser using a WYSIWYG text editor or simplified language called wikitext.

Wikipedia definition: A wiki is a website that allows the easy creation and editing of any number of interlinked web pages via a web browser using a simplified markup language or a WYSIWYG text editor.Wikis are typically powered by wiki software and are often used to create collaborative wiki websites, to power community websites, for personal note taking, in corporate intranets, and in knowledge management systems.

SOURCE : Altera Wiki , See also – http://www.alteraforum.com/

Altera’s 28-nm Variable-Precision DSP Block Architecture Wins the 2011 DesignVision Award

Altera Corporation (NASDAQ: ALTR) has announced that its variable-precision digital signal processing (DSP) block architecture won the DesignCon 2011 DesignVision Award in the Semiconductor and IC category. Altera’s variable-precision DSP block architecture was recognized by DesignVision Award judges for its ability to enable high-precision, high-performance digital signal processing in FPGAs that efficiently supports many different precision levels. This unique architecture is implemented within Altera’s portfolio of 28-nm FPGAs to increase system performance, reduce power consumption and reduce architecture constraints for DSP algorithm designers. Altera was presented with the 2011 DesignVision Award at a ceremony held at the Santa Clara Convention Center during DesignCon 2011.

Altera developed the industry’s first variable-precision DSP block architecture to meet the industry’s demands for higher precision signal processing. This innovative architecture allows each DSP block in the FPGA to be configured at compile time to three 9×9, two 18×18 or a single 27×27 or 18×36 multiplier mode. Additional higher precision modes are available using multiple DSP blocks. This architecture supports, on a block-by-block basis, various precisions per block, ranging from low resolution fixed point video up to single-precision floating point within a single DSP block, and even double-precision floating point with minimal external logic. To learn more about Altera’s variable-precision DSP block architecture, or to view a white paper or webcast on the architecture, visit www.altera.com/dsp-variable-precision.

SOURCE – Altera’s 28-nm Variable-Precision DSP Block Architecture Wins the 2011 DesignVision Award

dspblok™ – ADI SHARC & Altera Cyclone Hybrid Board

Want the power of DSP without the design and manufacturing burden? Danville Signal’s dspblok family of products combine an Analog Devices SHARC DSP with the supporting circuits necessary to implement a powerful DSP Function Module. Connections are brought out to standard 2mm dual row headers

Faster Time-to-Market Without the Risk

The dspblok™ substantially reduces development costs, risk and time. By taking advantage of the pretested signal processing module, pc board layouts become simpler and projects are completed quickly and cost effectively.
The dspblok™ gives you all the high performance, features, and peripheral support you want from a DSP without the need for a full custom design. And its compact size makes it a perfect fit for your embedded application.

For more details visit the Danville Website: http://www.danvillesignal.com/dspblok/dspblok.html