embedded

All Aboard the Small Form Factor Express

COM Express

Big is beautiful – or so we are told. But now it looks like small and petit is well and truly back in fashion.

SWAP – Size Weight And Power is the driving force behind many embedded applications today and low power, and often small footprint, processors such as those made by UK based ARM and Intel’s ATOM enable designs to shrink to very small proportions.

COM Express was ratified by PICMG in 2005, but now 6 years later the COM Express Mini / Ultra (or Nano ETX Express as Kontron would have us call it) is here and its tiny!

This new form factor is about the size of a credit card, specifically 55mm x 84mm and can have one of 2 connector configurations defined by the COM Express standard; both using a 220 pin connector.

• Type 1: Single connector (220 pin), 6 PCI Express lanes, no PEG, no PCI, no IDE, 4 SATA, 1 LAN
• Type 10: Single connector (220 pin), 4 PCI Express lanes, no PEG, no PCI, no IDE, 2 SATA, 1 LAN, single channel LVDS only, DDI, no VGA, 2 Serial COM

As you can see the focus is high speed PCI Express and Type 1 has 6 PCI Express lanes. But the more popular Type 10 maximises the variety and has a lower 4 PCI Express Lanes but adds Serial COMS, DDI (digital display interface) and LVDS.

A custom carrier board will need to be designed by the OEM to host the COM Express module but this can easily remain in the small footprint allowing the form factor to be used in ultra small, mobile and hand held applications. This enables new application opportunities that were previously inhibited by size, weight or power restrictions.

Applications – robotics, UAV, communications, computing, EPOS, handheld terminals and small rugged computers.

XPand6001 - Extreme Engineering

Sarsen Technology Limited is currently reviewing a range of COM Express modules for the UK market; if you have a project requirement or would like to know more about small form factor boards and chassis please get in touch via the website.

Links/References:
ARM – http://www.arm.com
ATOM – http://www.intel.com/…
Extreme Engineering – http://www.x-es.com
Image Credit – www.kontron.com

What is an FPGA?

What is an FPGA?

Increasingly FPGAs have gained popularity in the embedded market space to speed up development and for rapid prototyping of complex systems. But what is an FPGA? Here is a very good explanation from market leader Altera.

The field-programmable gate array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows you to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field—hence the name “field-programmable”. You can use an FPGA to implement any logical function that an application-specific integrated circuit (ASIC) could perform, but the ability to update the functionality after shipping offers advantages for many applications.

Unlike previous generation FPGAs using I/Os with programmable logic and interconnects, today’s FPGAs consist of various mixes of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. Specifically, an FPGA contains programmable logic components called logic elements (LEs) and a hierarchy of reconfigurable interconnects that allow the LEs to be physically connected. You can configure LEs to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flipflops or more complete blocks of memory.

As FPGAs continue to evolve, the devices have become more integrated. Hard intellectual property (IP) blocks built into the FPGA fabric provide rich functions while lowering power and cost and freeing up logic resources for product differentiation. Newer FPGA families are being developed with hard embedded processors, transforming the devices into systems on a chip (SoC).

Compared to ASICs or ASSPs, FPGAs offer many design advantages, including:

• Rapid prototyping
• Shorter time to market
• The ability to re-program in the field for debugging
• Lower NRE costs
• Long product life cycle to mitigate obsolescence risk

Source : http://www.altera.com/

Marvell Super Heroic Processors?

Marvell Armada XP

Founded in 1995, Marvell Technology Group Ltd. has operations worldwide and approximately 5,700 employees. They are a fabless semiconductor company, shipping over one billion chips a year. In their words:

“Marvell’s expertise in microprocessor architecture and digital signal processing, drives multiple platforms including high volume storage solutions, mobile and wireless, networking, consumer, and green products. Worldclass engineering and mixed-signal design expertise helps Marvell deliver critical building blocks to its customers, giving them the competitive edge to succeed in today’s dynamic market.”

My interest today is the Quad-Core ARMADA XP Series.

http://www.marvell.com/processors/embedded/armada_xp/assets/armada_xp_pb.pdf

The Extreme Performance (XP) series of multicore processors is a quad-core ARM processor designed primarilly for cloud computing applications. The ARMADA XP series integrates four Marvell designed ARM compliant 1.6GHz CPU cores along with a host of I/O peripherals to offer one of the highest levels of integration in the industry.

I am currently seeking out embedded projects that will require this low power CPU installed on XMC or VPX modules for military and defence applications. The ARMADA XP supports multiple SATA, USB and Ethernet ports as well as PCI-e 2.0 Ports and high speed SERDES lanes.

The processor is ideal of high speed multicore processing applications and integrated on the right platform will make a superb embedded processor for harsh environments.

THE MARVELL ADVANTAGE: Marvell chipsets come with complete reference designs which include board layout designs, software, manufacturing diagnostic tools, documentation, and other items to assist customers with product evaluation and production. Marvell’s worldwide field application engineers collaborate closely with end customers to develop and deliver new leading-edge products for quick time-to-market. Marvell utilizes world-leading semiconductor foundry and packaging services to reliably deliver high-volume and low-cost total solutions.

• Website – http://www.marvell.com
• YouTube – http://www.youtube.com/user/marvellmedia
• Twitter – http://twitter.com/marvellsemi

NVIDIA® Tesla™ GPU Computing Solutions

Trenton Technology brings over thirty years of design, manufacturing and system engineering experience to the world of High-Performance GPU Computing.

With an in-depth knowledge of high-speed bus technology, system BIOS, power requirements and shock, vibration and thermal characteristics is incorporated into every integrated computer system, single board computer, backplane and embedded motherboard.

Trenton are a member of the NVIDIA Tesla Preferred Partner (TPP) program Trenton is now creating computing solutions supporting NVIDIA’s Tesla GPU 20-series computing products and CUDA™ GPU architecture.

“Trenton’s design, engineering and integration capabilities are ideal for customers who require a high-performance computing solution based on industry-specific system requirements,” said Shanker Trivedi, vice president of sales, NVIDIA Professional Solutions Group. “These industry solutions are ideal platforms for implementing NVIDIA’s Tesla computing processors and CUDA GPU architecture.”

More – NVIDIA Tesla GPU Solutions from Trenton.

Raspberry Pi, The £15 Computer on a Stick

Raspberry Pi - Computer on a Stick

Apple have been using ARM processors iPODs for a number of years. The iPAD uses an ARM Cortex-A9-based CPU accompanied by a GPU. Sony’s next generation portable gaming device (PSP, NGP, VITA) to be launched at sometime later this year will also use an ARM processor.

The consumer and embedded marketplace simply wouldn’t be the same without ARM.

Today I read about something quite amazing on Electronics Weekly – Raspberry Pi is a tiny ARM-based single board computer that enables a TV to run Linux and scripting languages such as Python. Designed by Cambridge business men and academics to engage children with computer science and thereby improve the skills pool from which they draw employees and undergraduates, it is causing a stir in the developing world.

The result is a 32-bit ARM11-based computer than needs no supporting PC. The size of a USB stick, it has an HDMI connector on one end for the TV, a USB connector at the other end for the keyboard, and it boots immediately into Linux running a scripting language.

The company behind this amazing piece of hardware say they can buidl it for £15 each and its mission is: “To promote the study of computer science and related topics, especially at school level, and to put the fun back into learning computing”..

Further details can be found on the Raspberry Pi Foundation website and on Electronics weekly.

Source – http://www.electronicsweekly.com

Mobile Apps Bring Momentum to DRAMs

The huge success of tablet PCs and smart phones is driving sales in DRAM. Mobile “APPS” are big business, from pointless time wasting games and gimmicks to full blown business and organistaion tools – each requiring varying amounts of DRAM to run efficiently and effectively.

BBC’s The Apprentice even had the teams creating and selling Apps as a task this series.

The stakes are high in mobile memory. Before the onslaught of snazzy smartphones and tablets, mobile DRAM was considered the “sleepy backwater” in the memory market, said Mike Howard, an analyst at IHS iSuppli. Now, thanks to smartphones and tablets, the mobile DRAM sector is expected to grow by 71 percent in 2011, Howard said.

A mobile DRAM costs two to four times more than a PC DRAM because of mobile apps’ stringent size and power demands. The mobile DRAM business is based on a build-to-order model, with pricing driven by cost reductions rather than the fluctuations of supply and demand, as in commodity DRAM, IHS’ Howard said.

For more detailed info go to the SOURCE – Mobile apps bring momentum to DRAMs – EE Times.

Embedded Testing – Extreme Engineering Solutions

X-ES BIT

In any embedded and critical system, reliability is often the most important feature. X-ES Built-In Test (BIT) software provides exceptional test coverage through Power-On BIT (PBIT), Continuous BIT (CBIT) and Initiated BIT (IBIT) routines. Integrated as a standard component of X-ES Board Support Packages (BSPs), X-ES BIT software requires no additional purchase.

http://www.xes-inc.com/capabilities/software/bit/

Built-In Test (BIT) is a critical aspect of system reliability and maintainability. BIT support provides our customers with the capability to quickly detect, isolate, and determine the root cause of a potential problem within their system. Through the use of X-ES BIT, system reliability, maintainability, and operational availability can be improved. X-ES BIT is an open, extensible test platform that developers can incorporate into their system design to reduce the amount of development they need to do in order to meet their testing and diagnostic requirements.

What makes X-ES BIT Best In Class?

• Free with all current X-ES Intel and Freescale SBC’s
• BIT covers all of the major SBC functional blocks
• Standardized API across architectures and operating systems
• Written in ANSI C, licensed source code is included
• X-ES BIT supports Power-On BIT (PBIT),also known as Power-On Self Test (POST), Continuous BIT (CBIT), and Initiated BIT (IBIT)

You can follow Extreme Engineering Solutions on Twitter or View their website here – www.x-es.com

Epiphany Architecture Promises Massive Floating-Point Gains

Epiphany Architecture

Earlier this month BittWare announced “A New Approach to Floating Point DSP” with the release of the Anemone Co-Processor. The Anemone floating point co-processor chip is designed for use with Altera’s high performance FPGAs. OEM’d from Adapteva’s new Epiphany architecture, BittWare’s Anemone chip is a scalable, true C-programmable, floating point engine that enables novel solutions for complex and evolving signal processing applications.

It’s something which has already caught the eye of FPGA and DSP specialist BittWare, which has licensed Adapteva’s Epiphany technology for use in its own Altera-based FPGAs under the name Anemone. “We believe that Adapteva’s Epiphany architecture represents a flash of brilliance that reintroduces some much needed creativity into the embedded signal processing world,” BittWare’s chief Jeff Milrod crowed at the launch of Anemone. “The resulting Anemone chip, combined with Altera’s family of FPGAs, creates an insanely cool solution for complex signal processing tasks that can be optimised for power, performance, and productivity.”

So what is Epiphany? Here’s the opening section of an interview with Andreas Olofsson of Adapteva with THINQ:

While chip giants ARM, Intel, and AMD battle for control of your smartphones and PCs, a small company in Massachusetts called Adapteva is starting a revolution: many-core processors that offer a significant performance boost over anything currently on the market. We chat to its founder Andreas Olofsson to find out what’s going on.

Initially, it’s easy to dismiss Adapteva’s chances of success as slim to none: in markets where a single processor architecture holds overwhelming dominance, such as x86 in mainstream computing and ARM in the world of smartphones, Olofsson has decided to develop an entirely new architecture.

Olofsson readily admits that history is littered with companies who have tried the same approach and failed. “In the mobile space there’s MIPS, for example,” he explained to thinq_ during our interview. “That’s another architecture, which has been around for 25, 30 years now – you know, it’s a great architecture, and yet they have very low traction. Everybody – 98 per cent of the market – uses ARM.”

To avoid falling into the same trap, Olofsson has a new idea – or, specifically, a variation on an old one. In the early days of personal computing, it was common for a central processor to have a ‘math co-processor’ chip alongside it – a secondary processor which was designed specifically to carry out floating point arithmetic at speeds significantly faster than the main processor. Intel had its 8087, Motorola its 68881, and AMD the stand-alone 9511.

Over time, however, these chips became integrated into the processor itself – evolving into the high-performance floating-point units, or FPUs, that are a feature of all modern central processors. Olofsson’s big idea, he explained, is to bring the days of the math co-processor back – and promises some major performance-per-watt gains for those making the step.

Read more / Source – THINQ

See Also – Wall Street Journal, BittWare Anemone, Adapteva

Intel unveils 22nm 3D Ivy Bridge processor

Traditional planar chip design (left) and Intel's new Tri-Gate technology (right). The company believes that 3D transistors perform more efficiently

Intel has unveiled its next generation of microprocessor technology, code named Ivy Bridge.

The upcoming chips will be the first to use a 22 nanometre manufacturing process, which packs transistors more densely than the current 32nm system. Intel said it would also be using new Tri-Gate “3D” transistors, which are less power hungry. Rival chip manufacturers including AMD and IBM are understood to be planning similar designs. Conventional planar transistor Traditional microprocessor transistors are “planar” or flat as they pass through the switching gate.

Tri-Gate – Intel Tri-Gate diagram The Tri-Gate system features 3D “fins”. Intel claims the greater surface area improves efficiency.

The announcement marks a significant step forward in the commercial processor industry, which is constantly striving to build more transistors onto silicon chips. One of the main measures of its progress is the length of the transistor “gate”, measured in nanometres (1nm = 1 billionth of a meter). A human hair is around 60,000 nm wide. Current best microchip technology features a 32nm gate. It has been known for a long time that 22nm technology would form the next stage in the evolution of microprocessors. However, the exact nature of Intel’s offering has been a closely guarded secret, until now.

The company expects to begin commercial production later this year.

SOURCE – BBC – http://www.bbc.co.uk/news/technology-13283882

Anemone Co-Processor for FPGAs, BittWare Inc

Anemone Co-Processor for FPGAs

SAN JOSE, CALIFORNIA – May 3, 2011 – BittWare announced today, at the Embedded Systems Conference, the Anemone floating point co-processor chip for use with Altera’s high performance FPGAs.

Read the Full Press Release here: http://www.bittware.com/media/press/pr.cfm?id=62

BittWare yesterday introduced Anemone to the Embedded Systems Conference. What is it?

Its a Floating Point Co-Processor for FPGAs. Anemone represents a new hybrid approach for floating point signal processing that adds a low-power, C-programmable compute engine to world-class FPGA technology from Altera.

Features

• 16 independent floating point cores
• 32 GFLOPS of floating point processing
• 2 Watts total chip power
• ANSI C-programmable
• IEEE Floating Point
• Shared memory architecture
• External I/O via memory-mapped links
• Scale multiple chips up to 8 TFLOPS
• High throughput mesh network
• Standard GNU/Eclipse Development Tools
• Available from BittWare on standard board formats

For more information – visit the Anemone page on BittWare’s website.

Traditional floating point DSPs, while excellent at complex processing tasks, have limitations when it comes to chip real estate and power efficiency that have caused them to become an endangered species. And FPGAs, while superior for versatility and configurability, can be difficult to use for complex and evolving applications. The BittWare Anemone, featuring the Epiphany architecture from Adapteva, enables the best assets of both to be combined, thereby offering a completely new approach to floating point digital signal processing. This hybrid solution provides a standard processor software development environment working in conjunction with a world-class FPGA platform, allowing users to optimally partition their algorithms into hardware and software. The result is superior development productivity and unmatched system size, weight, and power.

Focus on power & efficiency

Anemone is a truly C-programmable floating point compute engine. It is unique in that it achieves superior power efficiency and processing performance because it is designed to work alongside an FPGA as a co-processor. The FPGA handles all the memory, I/O interfacing, protocol processing, and special functions in addition to any computational tasks it may perform, leaving the Anemone free to efficiently perform the complex processing tasks that DSPs are ideal for. This allows Anemone to be an extremely efficient chip – as compared with traditional floating point DSPs that may only use 5% of the silicon area for processing.

Simple, elegantly designed floating point cores

The Anemone is a completely scalable 1 GHz multicore processor with 16 eCores that provide a total sustained performance of 32 GFLOPS while consuming only 2 Watts of total chip power. Each eCore features a compact, general-purpose instruction set that requires no instruction level parallelism and provides high program efficiency. All floating point computations are performed as single-precision IEEE 754; hardware looping is also supported. Anemone offers distributed and segmented memory, and large uniform register files. On-chip distributed shared memory is 4 Mb (32 KByte per eCore) with 32 GBytes/sec of sustained memory bandwidth within each eCore. The cache-less shared memory architecture is extended off-chip via I/O links.

High-throughput eMesh network

The Anemone features an internal high-throughput mesh network, with separate data paths for on-chip and off-chip communications. Each eCore has a multi-channel DMA engine to support background data movement over the mesh. Total on-chip, inter-core bandwidth is 128 GBytes/sec full duplex, with an additional 8 GBytes/sec of off-chip bandwidth. Each router node can simultaneously sustain full-duplex transfers on all ports, with automatic routing based on global addressing.

I/O via memory-mapped high-speed links

The Anemone provides a flexible low-overhead external interconnect scheme that supports memory-mapped direct connection of multiple Anemones and is compatible with any LVDS capable FPGA. This is achieved via four links that are full-duplex 8-bit LVDS data ports @ 500 MHz DDR, each simultaneously providing 1 GByte/sec in each direction for a total off-chip bandwidth of 8 GBytes/sec. Its FPGA co-processor use model provides the ultimate flexibility: since all external I/O goes through an FPGA, system designers can customize the I/O to their application’s specific requirements.

ANSI C-programmable; Standard GNU development tools

The Anemone reduces system development cost by enabling out-of-the-box execution of applications written in regular ANSI-C. It does not require any C-subset, language extensions, or SIMD. Standard GNU development tools are supported including an optimizing C complier, simulator, GDB debugger, and Eclipse multi-core IDE.